I am Postdoctoral Researcher at Pohang University of Science and Technology (POSTECH), Korea. I am working with Professor Seokhyeong Kang at CAD & SoC Design Lab.
My current research interests include AI-driven EDA (Electronic Design Automation), physical design optimization, and deep learning hardware.
☎️ Contact Information
📧 [email protected]
🔗 LinkedIn
🔗 Google Scholar
👨🏻💻 Work Experiences
| Postdoctoral Researcher | 2026.03 - Present | POSTECH Institute of Artificial Intelligence (PIAI)
Advisor: Prof. Seokhyeong Kang |
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| Graduate Student Researcher | 2021.02 - 2026.02 | CAD & SoC Design Lab in POSTECH
Advisor: Prof. Seokhyeong Kang |
| Research Intern | 2023.06 - 2023.08 | Samsung Advanced Institute of Technology (SAIT)
ML TU, AIDA Team |
| Undergraduate Student Researcher | 2020.02 - 2021.02 | CAD & SoC Design Lab in POSTECH
Advisor: Prof. Seokhyeong Kang |
📚 Education
| M.S.-Ph.D. in Electrical Engineering | 2021.02 - 2026.02 | Pohang University of Science and Technology (POSTECH), Pohang, Republic of Korea
Advisor: Prof. Seokhyeong Kang
Dissertation: A Study on AI-Driven EDA for Efficient VLSI Physical Design: Leveraging Prediction, Generation, and Exploration |
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| B.S. in
Electrical Engineering | 2017.02 - 2021.02 | Pohang University of Science and Technology (POSTECH), Pohang, Republic of Korea |
📝 Publications
Conference
- [1] Jongho Yoon, Jinsung Jeon and Seokhyeong Kang, “Late Breaking Results: A Geometric Diffusion Model for Macro Placement Generation,” in 2025 62th ACM/IEEE Design Automation Conference (DAC), 2025.
- [2] Jongho Yoon, Jakang Lee, Donggyu Kim, Junseok Hur, and Seokhyeong Kang, “ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC Prediction,” in 2025 Asia and South Pacific Design Automation Conference (ASP-DAC), 2025.
- [3] Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, Seonghyeon Park, Jaemin Seo, Jongho Yoon, and Seokhyeong Kang, ”Leveraging Machine Learning Techniques to Enhance Traditional EDA Workflows”, in 2025 Asia and South Pacific Design Automation Conference (ASP‐DAC), 2025.
- [4] Haena Song, Jongho Yoon, Dohun Kim, Eunji Kwon, Tae Hyeon Oh, and Seokhyeong Kang, "FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks," in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023.
- [5] Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, and Youngjoo Lee, "Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor," in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022